1. Field
Various embodiments disclosed herein relate generally to methods of and systems for digital-to-analog conversion. This disclosure relates to methods of and systems for calibrating a digital-to-analog converter (DAC).
2. Background
DACs are utilized in a wide variety of applications. DACs can be susceptible to various types of errors including but not limited to errors related to current or voltage source mismatches, gain and offset errors, as well as errors caused by external signal paths. To achieve better performance in the areas of signal-to-noise and distortion ratio (SNDR), total harmonic distortion (THD), and spurious free dynamic range (SFDR), self-calibration techniques are utilized to calibrate the output provided by the DAC.
One self-calibration technique employs controllable current sources and a calibration circuit to tune current source values. The calibration circuit compares the current source value provided by a selected controllable current source to a reference current value and adjusts the controllable current source in accordance with the comparison. However, with such conventional self-calibration of current source values, DACs can be susceptible to large integral non-linearity (INL) errors across the bit elements of the DAC, which can result in large DAC performance variations. The large or unbounded INL errors can be due to calibration errors or variations. The calibration errors can be caused by finite calibration resolution, current comparator noise, and other issues.
According to another self-calibration technique, an analog-to-digital converter digitizes most significant bit (MSB) codes at the output of the DAC and compares the MSB codes to expected outputs to obtain errors which are stored for each code. The errors are used to drive the DAC and compensate for the errors. However, this ADC-based self-calibration technique requires an ADC with adequate resolution which significantly adds to the silicon area and power consumption of the DAC.